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HFA3724
Data Sheet November 1999 File Number 4067.7
400MHz Quadrature IF Modulator/Demodulator
The Intersil 2.4GHz PRISMTM chip set is a highly integrated five-chip solution for RF modems employing Direct Sequence Spread Spectrum (DSSS) signaling. The HFA3724 400MHz Quadrature IF Modulator/Demodulator is one of the five chips in the PRISMTM chip set (see the Typical Application Diagram).
TM
Features
* Integrates all IF Transmit and Receive Functions * Broad Frequency Range . . . . . . . . . . . 10MHz to 400MHz * I/Q Amplitude and Phase Balance . . . . . . . . . . . 0.2dB, 2o * 5th Order Programmable Low Pass Filter. . . . . . . . . . . . . . . . . . . 2.2MHz - 17.6MHz * 400MHz Limiting IF Gain Strip with RSSI. . . . . . . . . .84dB * Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm * Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . . 1s * Power Management/Standby Mode * Single Supply 2.7V to 5.5V Operation
The HFA3724 is a highly integrated baseband converter for quadrature modulation applications. It features all the necessary blocks for baseband modulation and demodulation of I and Q signals. It has a two stage integrated limiting IF amplifier with 84db of gain with a built in Receive Signal Strength Indicator (RSSI). Baseband antialiasing and shaping filters are integrated in the design. Four filter bandwidths are programmable via a two bit digital control interface. In addition, these filters are continuously tunable over a 20% frequency range via one external resistor. The modulator channel receives digital I and Q data for processing. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency of modulation/demodulation. A selectable buffered divide by 2 LO output and a stable reference voltage are provided for convenience of the user. The device is housed in a thin 80 lead TQFP package well suited for PCMCIA board applications.
Applications
* Systems Targeting IEEE 802.11 Standard * TDD Quadrature-Modulated Communication Systems * Wireless Local Area Networks * PCMCIA Wireless Transceivers * ISM Systems * TDMA Packet Protocol Radios
Ordering Information
PART NUMBER HFA3724IN HFA3724IN96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 80 Ld TQFP Tape and Reel PKG. NO. Q80.14x14
* PCS/Wireless PBX * Wireless Local Loop
Simplified Block Diagram
LPF_RX_Q LPF_RX_I LPF_TUNE_1 LPF_TUNE_0 MOD_RX_I MOD_RX_Q LIM2_OUT MOD_IF_IN LPF_SEL0 LPF_SEL1 LPF_RXI_OUT LPF_RXQ _OUT MOD_LO_IN /2 MOD_LO_OUT LO_GND MOD_TX_IF_OUT 2V REF MOD_TX_Q MOD_TX_I LPF_TX_Q LPF_TX_I 2V REF 0o/90o M U X I M U X LPF_TXI_IN LPF_TXQ_IN LIM1_OUT LIM2_IN LIM1_IN RSSI1 RSSI2 IF IF
Q
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
HFA3724 Pinout
80 LEAD TQFP TOP VIEW
LIM1_RSSI RSSI_RL1 GND LIM1_OUT+ LIM1_OUTLIM1_VCC LIM1_PE GND GND GND GND GND GND GND GND GND LIM2_BYPLIM2_INLIM2_IN+ LIM2_BYP+ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 LIM1_BYP+ LIM1_IN+ LIM1_INLIM1_BYPGND GND GND GND LPF_VCC 2V REF LPF_BYP LPF_TXI_IN LPF_TXQ_IN LPF_RXI_OUT LPF_RXQ_OUT LPF_SEL1 LPF_SEL0 LPF_TUNE1 LPF_TUNE0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LPF_RX_PE LPF_TX_PE LPF_TXQLPF_TXQ+ LPF_TXILPF_TXI+ LPF_RXQLPF_RXQ+ LPF_RXILPF_RXI+ GND GND MOD_RXI+ MOD_RXIMOD_RXQ+ MOD_RXQMOD_TXI+ MOD_TXIMOD_TXQ+ MOD_TXQ60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 LIM2_RSSI RSSI_RL2 GND LIM2_OUT+ LIM2_OUTLIM2_VCC LIM2_PE GND GND GND LO_GND MOD_IF_INMOD IF_IN+ MOD_VCC MOD_LO_OUT MOD_VCC MOD_LO_IN MOD_RX_PE MOD_TX_IF_OUT MOD_TX_PE
2
HFA3724 Block Diagram
LPF_RXI_OUT
LPF_RXQ_OUT
LPF_SEL1 LPF_SEL0 LPF_TUNE0 LPF_TUNE1 LPF_RX PE LPF_RX I LPF_RX I + LPF_RX Q + LPF_RX Q MOD_RX Q MOD_RX Q + MOD_RX I MOD_RX I + DOWN CONV 90o Q I MUX MUX_LPF LPF_TX_PE
LPF_TXQ_IN
LPF_TXI_IN
LPF_TX_Q LPF_TX_Q + LPF_TX_I LPF_TX_I +
MUX
MOD TX I + MOD TX I MOD TX Q + MOD TX Q -
MOD_RX PE
/
MOD_IF_IN + MOD_IF_IN LIM2_OUT LIM2_OUT + LIM2_PE LIM2_IN+ LIM2_INIF LIMITERS LIM1_OUT LIM1_OUT + LIM1_PE IF
/2
0o
MOD_TX_PE
UP CONVERTER
2V REF
2V REF
IF
LIM1_INLIM1_RSSI RSSI_RL1
RSSI_RL2 LIM2_RSSI
LPF_BYP MOD_TX IF_OUT 1.25V
LIM1_IN+
LO_GND
SAW
(2XLO)
IF IN
MOD_LO_IN
RSSI
NOTE: VCC, GND and Bypass capacitors not shown.
3
MOD_LO_OUT
50
VCC
HFA3724 Typical Application Diagram
HFA3724
(FILE# 4067)
TUNE/SELECT
HSP3824
(FILE# 4064)
RXI DATA TO MAC CTRL SPREAD DPSK MOD. PRISMTM CHIP SET FILE #4063
HFA3424 (NOTE)
(FILE# 4131)
A/D DESPREAD
DPSK DEMOD
HFA3624 RF/IF CONVERTER
(FILE# 4066)
I
RXQ
A/D CCA 802.11 MAC-PHY INTERFACE
/2
0o/90o
M U X
M U X
RSSI
A/D TXI
RFPA
HFA3925
(FILE# 4132)
VCO
VCO
TXQ Q
QUAD IF MODULATOR DUAL SYNTHESIZER
DSSS BASEBAND PROCESSOR
HFA3524 (FILE# 4062)
TYPICAL TRANSCEIVER APPLICATION USING THE HFA3724 NOTE: Required for systems targeting 802.11 specifications.
For additional information on the PRISMTM chip set, call (407) 724-7800 to access Intersil' AnswerFAX system. When prompted, key in the four-digit document number (File #) of the datasheets you wish to receive. The four-digit file numbers are shown in Typical Application Diagram, and correspond to the appropriate circuit.
4
HFA3724 Typical Application Diagram
VCC 0.1 75 PE 74 2 260 3 1 4 100p 77 76 100p 80 (NOTE 2) 8 TO 40p 10nH 100p VCC 0.1 55 100p 560 0.1 100p 62 63 61 100p 64 100p 59 (NOTE 3) CONVERTER HFA3624IA 47p 220 44 LO_IN 56 47p 35 0.01 28 36 0.01 18 900 19 (NOTE 5) 46 37 0.1 TOYOCOM TQS 432 IF/RF TX_IF_OUT 47nH VCC 316 42 38 0.01 39 0.01 24 40 50 NC 560MHz VCO (AUXILIARY) 43 41 0.01 22 23 0.01 10 2V REF 26 25 12 4.3K 680 0.1 11 680 TXQ 13 4.3K LPF_TX_PE LPF_RX_PE 21 TXI 0.1 16 LPF_SEL1 VCC 17 LPF_SEL0 27 PE 54 57 100p 56 1K 45 48 49 47 9 RXI_OUT 0.01 0.1
(Targeting IEEE 802.11 Standard)
VCC 0.1 VCC RSSI
TOYOCOM TQS 432 RF/IF
(NOTE 1) 100p 56n
33 0.01 30 34 0.01 29
14
0.1 100p 100p
60 100p
47p 79
15 20
RXQ_OUT 0.01
(NOTE 6)
100p 47
100p (NOTE 4)
VCO
DUAL SYNTHESIZER HFA3524IA
TYPICAL APPLICATION DIAGRAM (TARGETING IEEE 802.11 STANDARD) NOTES: 1. Input termination used to match a SAW filter. 2. Typical bandpass filter for 280MHz, BW = 47MHz, Q = 6. Can also be used if desired after the second stage. 3. Network shown for a typical -10dBm input at 50. 4. Output termination used to match a SAW filter. 5. RTUNE value for a 7.7MHz cutoff frequency setting. 6. LO buffer output termination is needed only when the buffer is enabled by pin 50 connected to GND, otherwise tie pin 46 to pin 47.
5
MOD_RX_PE
MOD_TX_PE
BASEBAND PROCESSOR HSP3824VI
HFA3724 Pin Description
PIN 1 2 3 4 5, 6, 7, 8 9 10 11 12 13 14 15 16 17 SYMBOL LIM1_BYP+ LIM1_In+ LIM1_InLIM1_BYPGND LPF_VCC 2V REF LPF_BYP LPF_TXI_In LPF_TXQ_In LPF_RXI_Out LPF_RXQ_Out LPF_Sel1 LPF_Sel0 DESCRIPTION DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. Non inverting analog input of Limiter amplifier 1. Inverting input of Limiter amplifier 1. DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. Ground. Connect to a solid ground plane. Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin. Stable 2V reference voltage output for external applications. Loading must be higher than 10k. A bypass capacitor of at least 0.1F is required. Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires 0.1F decoupling capacitor. Low pass filter in phase (I) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs. (Note 7) Low pass filter quadrature (Q) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs. (Note 7) Low pass filter in phase (I) channel receive output. Requires AC coupling. (Note 8) Low pass filter quadrature (Q) channel receive output. Requires AC coupling. (Note 8) Digital control input pins. Selects four programed cut off frequencies for both receive and transmit channels. Tuning speed from one cutoff to another is less than 1s. SEL1 SEL0 Cutoff Frequency SEL1 SEL0 Cutoff Frequency LO LO 2.2MHz HI LO 8.8MHz LO HI 4.4MHz HI HI 17.6MHz These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two pins (RTUNE) will fine tune both transmit and receive filters. Refer to the tuning equation in the LPF AC specifications. Ground. Connect to a solid ground plane. Digital input control pin to enable the LPF receive mode of operation. Enable logic level is High. Digital input control pin to enable the LPF transmit mode of operation. Enable logic level is High. Negative output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the inverting input of the quadrature Modulator (Mod_TXQ-), pin 40. Positive output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the non inverting input of the quadrature Modulator (Mod_TXQ+), pin 39. Negative output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the inverting input of the in phase Modulator (Mod_TXI-), pin 38. Positive output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the non inverting input of the in phase Modulator (Mod_TXI+), pin 37. Low pass filter inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the negative output of the quadrature demodulator (Mod_RXQ-), pin 36. Low pass filter non inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the positive output of the quadrature demodulator (Mod_RXQ+), pin 35. Low pass filter inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the negative output of the in phase demodulator (Mod_RXI-), pin 34. Low pass filter non inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the positive output of the in phase demodulator (Mod_RXI-), pin 33. Ground. Connect to a solid ground plane.
18 19 20 21 22 23 24 25 26 27 28 29 30 31, 32
LPF_Tune1 LPF_Tune0 GND LPF_RX_PE LPF_TX_PE LPF_TXQLPF_TXQ+ LPF_TXILPF_TXI+ LPF_RXQLPF_RXQ+ LPF_RXILPF_RXI+ GND
6
HFA3724 Pin Description
PIN 33 34 35 36 37 38 39 40 41 42 43 44 SYMBOL Mod_RXI+ Mod_RXIMod_RXQ+ Mod_RXQMod_TXI+ Mod_TXIMod_TXQ+ Mod_TXQMod_TX_PE Mod_TX_IF_Out Mod_RX_PE Mod_LO_In (2XLO) (Continued) DESCRIPTION In phase demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXI+), pin 30. In phase demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXI-), pin 29. Quadrature demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXQ+), pin 28. Quadrature demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXQ+), pin 27. In phase modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXI+), pin 26. In phase modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXI-), pin 25. Quadrature modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXQ+), pin 24. Quadrature modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXQ-), pin 23. Digital input control to enable the Modulator section. Enable logic level is High for transmit. Modulator open collector output, single ended. Termination resistor to VCC with a typical value of 316. Digital input control to enable the demodulator section. Enable logic level is High for receive. Single ended local oscillator current input. Frequency of input signal must be twice the required modulator carrier and demodulator LO frequency. Input current is optimum at 200ARMS. Input matching networks and filters can be designed for a wide range of power and impedances at this port. Typical input impedance is 130.This pin requires AC coupling. (Note 9) NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy. Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin. Divide by 2 buffered output reference from "Mod_LO_in" input. Used for external applications where the modulating and demodulating carrier reference frequency is required. 50 single end driving capability.This output can be disabled by use of pin 50. AC coupling is required, otherwise tie to pin 47 (VCC). Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin. Demodulator non inverting input. Requires AC coupling. Demodulator inverting input. Requires AC coupling. When grounded, this pin enables the LO buffer (Mod_LO_Out). When open (NC) it disables the LO buffer. Ground. Connect to a solid ground plane. Digital input control to enable the limiter amplifier 2. Enable logic level is High. Limiter amplifier 2 supply pin. Use high quality decoupling capacitors right at the pin. Positive output of limiter amplifier 2. Requires AC coupling. Negative output of limiter amplifier 2. Requires AC coupling. Ground. Connect to a solid ground plane. Load resistor to ground. Nominal value is 6k. This load is used to terminate the LIM RSSI current output and maintain temperature and process variation to a minimum. Current output of RSSI for the limiter amplifier 2. Connect in parallel with the RSSI output of the amplifier limiter 1 for cascaded response. DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. Non inverting analog input of Limiter amplifier 2.
45 46
Mod_VCC Mod_LO_Out
47 48 49 50 51, 52, 53 54 55 56 57 58 59 60 61 62
Mod_VCC Mod_IF_In+ Mod_IF InLO_GND GND LIM2_PE LIM2_VCC LIM2_OutLIM2_Out+ GND RSSI_RL2 LIM2_RSSI LIM2_BYP+ LIM2_In+
7
HFA3724 Pin Description
PIN 63 64 65, 66, 67, 68, 69, 70, 71, 72, 73 74 75 76 77 78 79 80 NOTES: 7. The HFA3724 generates a lower sideband signal when the "I" input leads the "Q" input by 90 degrees. 8. For a reference LO frequency higher than a CW IF signal input, the "I" channel leads the "Q" channel by 90 degrees. 9. The in-phase reference LO transitions occur at the rising edges of the 2XLO clock signal. Quadrature LO transitions occur at the falling edges. 180 degrees phase ambiguity is expected for carrier locked systems without differential encoding. TABLE 1. POWER MANAGEMENT TRANSMIT LIM1_PE LIM2_PE LPF_RX_PE MOD_RX_PE MOD_TX_PE LPF_TX_PE 0 0 0 0 1 1 RECEIVE 1 1 1 1 0 0 POWER DOWN 0 0 0 0 0 0 SYMBOL LIM2_InLIM2_BYPGND Inverting input of Limiter amplifier 2. DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. Ground. Connect to a solid ground plane. (Continued) DESCRIPTION
LIM1_PE LIM1_VCC LIM1_OutLIM1_Out+ GND RSSI_RL1 LIM1_RSSI
Digital input control to enable the limiter amplifier 1. Enable logic level is High. Limiter amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin. Negative output of limiter amplifier 1. Requires AC coupling. Positive output of limiter amplifier 1. Requires AC coupling. Ground. Connect to a solid ground plane. Load resistor to ground. Nominal value is 6k. This load is used to terminate the LIM RSSI current output and maintain temperature and process variation to a minimum. Current output of RSSI for the limiter amplifier 1. Connect in parallel with the RSSI output of the amplifier limiter 2 for cascaded response.
8
HFA3724
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Thermal Information
Thermal Resistance (Typical, Note 10) JA (oC/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Package Power Dissipation at 70oC TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1W Maximum Junction Temperature (Plastic Package . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . -65oC TA 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (TQFP - Lead Tips Only)
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40oC TA 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 10. JA is measured with the component mounted on an low effective thermal conductivity test board in free air. See Technical Brief 379 for details.
DC Electrical Specifications
VCC = 2.7V to 5.5V, Unless Otherwise Specified (NOTE 11) TEST LEVEL A A A A A A A A B B A B B C TEMP (oC) Full Full Full Full Full 25 25 25 25 25 Full 25 25 25
PARAMETER Total Supply Current, RX Mode at 5.5V Total Supply Current, TX Mode at 5.5V Shutdown Current at 5.5V All Digital Inputs VIH (TTL Threshold for All VCC) All Digital Inputs VIL (TTL Threshold for All VCC) High Level Input Current at 2.7V VCC, VIN = 2.4V High Level Input Current at 5.5V VCC, VIN = 4.0V Low Level Input Current, VIN = 0.8V RX to TX/TX to RX Switching Speed (Figure 23) Power Down/Up Switching Speed (Figure 23) Reference Voltage Reference Voltage Variation Over Temperature Reference Voltage Variation Over Supply Voltage Reference Voltage Minimum Load Resistance NOTE:
SYMBOL RXICC TXICC ICCOFF VIH VIL IIHI IIHh IIL PEt PEtpd VREF VREFT VREFV VREFRL
MIN 2.0 -0.2 -20 1.87 10
TYP 70 60 0.8 2 10 2.0 800 1.6 -
MAX 105 80 2.0 VCC 0.8 80 400 +20 2.13 -
UNITS mA mA mA V V A A A s s V V/oC mV/V k
11. A = Production Tested, B = Based on Characterization, C = By Design
AC Electrical Specifications, Demodulator Performance
Application Targeting IEEE 802.11, VCC = 3V, Figure 23 Unless Otherwise Specified (NOTE 12) TEST LEVEL B A C A A A B B TEMP (oC) 25 Full 25 Full Full Full 25 25
PARAMETER IF Demodulator 3dB Limiting Sensitivity (Note 13) IF Demodulator I and Q Outputs Voltage Swing IF Demodulator I and Q Channels Output Drive Capability (ZOUT = 50) CMAX = 10pF IF Demodulator I/Q Amplitude Balance, IFin = -70dbm at 50 IF Demodulator I/Q Phase Balance, IFin = -70dbm at 50 IF Demodulator Output Variation at -70dbm to 0dbm input IF Demodulator RSSI Noise Induced Offset Voltage (Note 14) IF Demodulator RSSI Voltage Output Slope (Note 15)
SYMBOL D3db DIQsw Doutz Dabal Dphbal Dovar Drssio Drssis
MIN 300 1.2 -1.0 -4.0 -0.5 -
TYP -84 460 2 0 0 0 580 15
MAX 650 +1.0 +4.0 +0.5 -
UNITS dBm mVP-P k dB Degrees dB mVDC mV/dB
9
HFA3724
AC Electrical Specifications, Demodulator Performance
Application Targeting IEEE 802.11, VCC = 3V, Figure 23 Unless Otherwise Specified (Continued) (NOTE 12) TEST LEVEL A A B B TEMP (oC) Full Full 25 25
PARAMETER IF Demodulator RSSI DC Level, Pin = -30dBm (Note 15) IF Demodulator RSSI DC Level, Pin = -70dBm (Note 15) IF Demodulator RSSI Linear Dynamic Range (Note 16) IF Demodulator RSSI Rise and Fall Time from -30dBm to -50dBm Input at 100pF Load NOTES:
SYMBOL Drssi_30 Drssi_70 Drssidr Drssitr
MIN 0.90 0.456 -
TYP 1.46 0.86 60 0.3
MAX 1.71 0.99 -
UNITS VDC VDC dB s
12. A = Production Tested, B = Based on Characterization, C = By Design 13. 2XLO input = 572MHz, measure IF input level required to drop the I and Q output at 6MHz by 3dB from a reference output generated at IF input = -30dBm (hard limiting). LPF selected for 8.8MHz. This is a noise limited case with a BW of 47MHz. Please refer to the Overall Device Description, IF limiter. 14. The residual DC voltage generated by the RSSI circuit due to a noise limited stage at the end of the chain with no IF input. IF port terminated into 50. Please referred to the Overall Device Description, IF limiter. 15. Both limiter RSSI current outputs are summed by on chip 6K resistors in parallel. 16. Range is defined where the indicated received input strength by the RSSI is 3dBm accurate.
AC Electrical Specifications, Modulator Performance
Application Targeting IEEE 802.11, VCC = 3V, Figure 23 Unless Otherwise Specified (NOTE 17) TEST LEVEL B B A A A B B A A A A B B TEMP (oC) 25 25 Full Full Full 25 25 Full Full Full Full 25 25
PARAMETER IF Modulator I/Q Amplitude Balance (Note 18) IF Modulator I/Q Phase Balance (Note 18) IF modulator SSB Output Power (Note 19) IF Modulator Side Band Suppression (Note 19) IF Mod Carrier Suppression (LO Buffer Enabled) (Note 19) IF Mod Carrier Suppression (LO Buffer Disabled) (Note 19) IF Modulator Output Noise Floor (Out of Band) IF Modulator I/Q 3dB Cutoff SEL0/1 = 2.2MHz (Note 20) IF Modulator I/Q 3dB Cutoff SEL0/1 = 4.4MHz (Note 20) IF Modulator I/Q 3dB Cutoff SEL0/1 = 8.8MHz (Note 20) IF Modulator I/Q 3dB Cutoff SEL0/1 = 17.6MHz (Note 20) IF Modulator Spread Spectrum Output Power (Note 21) IF Modulator Side Lobe to Main Lobe Ratio, LPF = 8.8MHz (Note 21) NOTES:
SYMBOL Mabal Mphbal Mssbpw Mssbss Mssbcs Mssbcs1 Moutn0 Msel1f Msel2f Msel3f Msel4f Mdsspw Mdsssl
MIN -1.0 -4.0 -12 26 28 28 1.8 3.6 7.3 14.6 -12 -
TYP 0 0 -7 33 30 36 -132 2.2 4.4 8.8 17.6 -7 35
MAX +1.0 +4.0 -4 2.5 5.0 9.8 19.6 -4 -
UNITS dB Degrees dBm dBc dBc dBc dBm/Hz MHz MHz MHz MHz dBm dB
17. A = Production Tested, B = Based on Characterization, C = By Design 18. Data is characterized by DC levels applied to MOD TXI and Q pins for 4 quadrants with LO output as reference or indirectly by the SSB characteristics. 19. Power at the fundamental SSB frequency of two 6MHz, 90 degrees apart square waves applied at TXI and TXQ inputs. VIH = 3.0V, VIL = 0.5V. LPF selected to 8.8MHz cutoff. 20. Cutoff frequencies are specified for both modulator and demodulator as the filter bank is shared and multiplexed for Transmit and Receive. Data is characterized by observing the attenuation of the fundamental of a square wave digital input swept at each channel separately. The IF output is down converted by an external wideband mixer with a coherent LO input for each of quadrature signals separately. 21. Typical ratio characterization with RTUNE set to 7.7MHz, LPF selected for 8.8MHz. TXI and TXQ Digital Inputs at two independent and aligned 11M chip/s, 223-1 sequence code signals.
10
HFA3724 Typical Performance Curves, Demodulator
10mA/DIV. 90 SUPPLY CURRENT (mA) OUTPUT SWING (mVP-P) 85o 25o -40o 400
(See Figure 23 Test Diagram)
50mV/DIV.
100
10 2.5 4.0 VCC 5.5 -100 -80
VCC = 3V
-60 -40 -20 INPUT POWER (dBm INTO 50)
0
FIGURE 1. DEMODULATOR SUPPLY CURRENT vs VCC AND TEMPERATURE
40mV/DIV. 700 85o 25o -40o
FIGURE 2. DEMODULATOR I/Q OUTPUT SWING vs INPUT POWER
1dBm/DIV. -80 -3dB SENSITIVITY (dBm INTO 50)
OUTPUT SWING (mVP-P)
500
-85
85o 25o -40o
300 2.5
4.0 VCC
5.5
-90 2.5
4.0 VCC
5.5
FIGURE 3. DEMOD I/Q OUTPUT SWING vs VCC AND TEMPERATURE
FIGURE 4. CASCADED LIMITER -3dB INPUT SENSITIVITY RESPONSE vs VCC AND TEMPERATURE
AMPLITUDE BALANCE VARIATION
0.2o/DIV. +1o PHASE BALANCE VARIATION
0.1dB/DIV. +0.4dB
0o
EXPECTED VARIATION WINDOW vs VCC
0.0dB
EXPECTED VARIATION WINDOW vs VCC
-0.4dB -1o 2.5 4.0 VCC 5.5 2.5 4.0 VCC 5.5
FIGURE 5. DEMOD I/Q PHASE BALANCE VARIATION vs VCC
FIGURE 6. DEMOD I/Q AMPLITUDE BALANCE VARIATION vs VCC
11
HFA3724 Typical Performance Curves, Demodulator
0.4dB/DIV. +2o AMPLITUDE BALANCE VARIATION +0.4dB PHASE BALANCE VARIATION
(See Figure 23 Test Diagram) (Continued)
0.1dB/DIV.
0o
EXPECTED VARIATION WINDOW vs TEMP
0.0dB
EXPECTED VARIATION WINDOW vs TEMP
-0.4dB -60 -40 -20 0 20 40 TEMPERATURE 60 80 100
-2o -60 -40 -20 0 20 40 TEMPERATURE 60 80 100
FIGURE 7. DEMOD I/Q PHASE BALANCE VARIATION vs TEMPERATURE
FIGURE 8. DEMOD I/Q AMPLITUDE BALANCE VARIATION vs TEMPERATURE
100mV/DIV. 1.5V
100mV/DIV. 1.4V 85o 25o -40o 1.0V
RSSI DC LEVEL
1.0V
RSSI DC LEVEL
VCC = 3V 0.5V -100
IF INPUT = -50dBM 0.6V 0 2.5 4.0 VCC 5.5
-80 -40 -20 -60 INPUT POWER (dBm INTO 50)
FIGURE 9. DEMOD RSSI DC LEVEL vs INPUT POWER
FIGURE 10. DEMOD RSSI DC LEVEL vs VCC AND TEMPERATURE
100mV/DIV. 900mV
85o 25o -40o
DC OFFSET
500mV
100mV 2.5 4.0 VCC 5.5
FIGURE 11. DEMODULATOR RSSI DC OFFSET vs VCC AND TEMPERATURE
12
HFA3724 Typical Performance Curves, Modulator
10mA/DIV. 90mA
(See Figure 23 Test Diagram)
10dB/DIV. -7dBm
SUPPLY CURRENT
85o 25o -40o
10mA 2.5 4.0 VCC 5.5 BW = 100kHz VBW = 30kHz 274MHz
280MHz FREQUENCY
286MHz
FIGURE 12. MODULATOR SUPPLY CURRENT vs VCC AND TEMPERATURE
FIGURE 13. TYPICAL SSB MODULATOR RESPONSE (NOTE 3 ON AC ELECTRICAL SPECIFICATIONS, MODULATOR PERFORMANCE TABLE, LO BUFFER ENABLED)
0.5dB/DIV. -4 OUTPUT POWER (dBm AT 50) 85o 25o -40o
1dB/DIV. +5dB SIDE BAND SUPPRESSION VARIATION FROM NOMINAL
0dB
EXPECTED VARIATION WINDOW
-9 2.5
4.0 VCC
5.5
-5dB 2.5
4.0 VCC
5.5
FIGURE 14. MODULATOR SSB OUTPUT POWER vs VCC AND TEMPERATURE
FIGURE 15. MODULATOR SSB SIDE BAND SUPPRESSION VARIATION vs VCC AND TEMPERATURE
0.5dB/DIV. -13 LO OUTPUT POWER (dBm AT 50) 85o 25o
SIDE BAND SUPPRESSION VARIATION FROM NOMINAL
1dB/DIV. +5dB
0dB
EXPECTED VARIATION WINDOW
-15.5
-40o
-5dB 2.5
4.0 VCC
5.5
-18 2.5
4.0 VCC
5.5
FIGURE 16. MODULATOR LO LEAKAGE VARIATION vs VCC AND TEMPERATURE
FIGURE 17. MODULATOR LO OUTPUT POWER (FUNDAMENTAL) vs VCC AND TEMPERATURE
13
HFA3724 Typical Performance Curves, Modulator
0dB
(See Figure 23 Test Diagram) (Continued)
PERCENT OF NOMINAL FREQUENCY
+20%
-3dB 1dB/DIV.
-20% -30 -25 -20 -15 -10 -5 0 +5 +10 +15 +20 +25 +30 [(787-RTUNE)/RTUNE] * 100%
1MHz
2MHz
10MHz
FIGURE 18. TYPICAL MODULATOR I/Q 3dB CUTOFF FREQUENCY CURVES
FIGURE 19. LPF CUTOFF FREQUENCY vs RTUNE, VCC = 3V, TA = 25oC
-24dBm
2%/DIV. +10%
PERCENT OF CUTOFF
0%
10dB/DIV.
-10% -60
-40
-20
0 20 40 TEMPERATURE
60
80
100
SPAN 50MHz BW = 300kHz VBW = 1kHz 280MHz
FIGURE 20. LPF CUTOFF FREQUENCY vs TEMPERATURE AND VCC (NOTE 4 ON AC ELECTRICAL SPECIFICATIONS, MODULATOR PERFORMANCE TABLE)
FIGURE 21. TYPICAL MODULATOR SPREAD SPECTRUM OUTPUT 11M CHIPS/s, QPSK. RTUNE TO 7.7MHz, 8.8MHz SETTING
-24dBm
10dB/DIV.
SPAN 50MHz BW = 300kHz VBW = 1kHz 280MHz
FIGURE 22. TYPICAL MODULATOR SPREAD SPECTRUM OUTPUT WITH RTUNE TO +20% OF 4.4MHz SETTING FOR ILLUSTRATION PURPOSES ONLY
14
HFA3724 Test Diagram (280MHz IF)
VCC 0.1 75 PE 74 2 3 0.1 1 100p 100p 100p 4 77 76 80 100p 100p 61 100p 64 100p 59 79 LO_IN 56 47p (NOTE 24) 47p 220 44 35 0.001 28 36 0.001 18 1K 19 100p RSSI LO_OUT (NOTE 25) 0.1 47nH TX_IF_OUT 3 TO 10p 50 VCC 316 42 37 0.001 26 38 0.001 39 0.001 24 40 0.001 23 25 12 4.3K 50 680 (NOTE 26) 0.1 11 680 (NOTE 26) 13 4.3K 50 22 LPF_TX_PE 21 LPF_RX_PE TXQ 46 16 LPF_SEL1 17 LPF_SEL0 10 2V REF 0.1 TXI 27 15 0.001 RXQ_OUT HI_Z_PROBE (NOTE 23) 8 TO 40p 10nH 0.1 55 100p 57 100p 560 0.1 62 63 56 60 100p 1K 48 49 33 0.001 30 34 0.001 29 14 0.001 RXI_OUT HI_Z_PROBE PE 54 45 47 9 100p VCC 0.1 VCC 0.1 VCC
(NOTE 22) IF_IN 100p 56
47p
TABLE 2. POWER MANAGEMENT TRANSMIT LIM1_PE LIM2_PE LPF_RX_PE MOD_RX_PE MOD_TX_PE LPF_TX_PE 0 0 0 0 1 1 RECEIVE 1 1 1 1 0 0 POWER DOWN 0 0 0 0 0 0
43 MOD_RX_PE
41 MOD_TX_PE
NOTES: 22. Input termination used to provide a 50 impedance. Limiter Noise Figure 9dB for this configuration. 23. Bandpass filter for 280MHz, BW = 47MHz, Q = 6. 24. Network shown for a typical -10dBm input at 50. 25. Matching network from 250 to 50 at 280MHz. 26. Attenuator is optional if TTL driver can drive 50. FIGURE 23. TEST DIAGRAM (280MHz IF)
15
HFA3724 Overall Device Description
The HFA3724 is a highly integrated baseband converter for half duplex wireless data applications. It features all the necessary blocks for baseband modulation and demodulation of "I" and "Q" quadrature multiplexing signals. It targets applications using all phase shift types of modulation (PSK) due to its hard limiting receiving front end. Four fully independent blocks adds flexibility for numerous applications covering a wide range of IF frequencies. A differential design architecture, device pin out and layout have been chosen to improve system RF properties like common mode signal immunity (noise, crosstalk), reduce relevant parasitics and settling times and optimize dynamic range for low power requirements. Single power supply requirements from 2.7VDC to 5.5VDC makes the HFA3724 a good choice for portable transceiver designs. The HFA3724 has a two stage integrated limiting IF amplifier with frequency response to 400MHz. These amplifiers exhibit a -84dbm, -3db cascaded limiting sensitivity with a built in Receive Signal Strength Indicator (RSSI) covering 60db of dynamic range with excellent linearity. An up conversion and down conversion pair of quadrature doubly balanced mixers are available for "I" and "Q" baseband IF processing. These converters are driven by an internal quadrature LO generator which exhibits a broadband response with excellent quadrature properties. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency for modulation/demodulation. Duty cycle and signal purity requirements for the 2X LO input using this type of quadrature architecture are less restrictive for the HFA3724. Ground reference input signals as low as -15dBm and frequencies up to 900MHz (2XLO) can be used and tailored by the user. A buffered, divide by 2, LO single ended 50 selectable output is provided for convenience of PLL designs. The receive channel mixers "I" and "Q" quadrature outputs have a frequency response up to 30MHz for baseband signals and the transmit mixers are summed and amplified to a single ended open collector output with frequency response up to 400MHz. Multiplexed or half duplex baseband 5th order Butterworth low pass filters are also included in the design. The "I" and "Q" filters address applications requiring low pass and antialiasing filtering for external baseband threshold comparison or simple analog to digital conversion in the receive channel. During transmission, the filter is used for pulse shaping or control of spectral mask. Four filter bandwidths are programmable, (2.2MHz, 4.4MHz, 8.8MHz and 17.6MHz) via a two bit digital or hardwired control interface. These cut off frequencies are selected for optimization of spectrum output responses for 2.25M, 5.5M, 11M and 22M chips/sec respectively for spread spectrum applications (These rates can also be interpreted as symbol rates for conventional data transmission). External processing 16 correlators in the receive channel as in the Intersil HSP3824 baseband converter, will bring the demodulation to lower effective data rates. As an example, the use of 11M chips/sec, 11 chip Barker code using the 8.8MHz low pass filter in a QPSK type of modulation scheme will bring a post processed effective data rate to 1M symbol/sec or 2M bits/sec. Likewise, the use of a 2.4M chips/sec, 16 chip spreading code and the use of 2.2MHz filter can process an effective data rate of 150K symbols/sec or 300K bits/sec. In addition, these filters are continuously tunable over a 20% frequency range via one external resistor. This feature gives the user the ability to reshape the spectrum of a transmitted signal at the antenna port which takes into account any spectral regrowth along the transmitter chain. The modulator "I" and "Q" filter inputs accept digital signal levels data for modulation and their phase and gain characteristics, including I / Q matching and group delay are well suitable for reliable data transmission. In the Receive mode and over the full input limiting dynamic range, both low pass filters outputs swing a 500mVP-P baseband signal. Each block has its own independent power enable control for power management and half duplex transmit/receive operation. A stable 2V DC output and a buffered band gap reference voltage are also provided for an external analog to digital conversion reference.
Detailed Description
(Refer to Block Diagram)
IF Limiter
Two independent limiting amplifiers are available in the HFA3724. Each one exhibits a broadband response to 400MHz with 45dB of gain. The low frequency response is limited by external components because the device has no internal coupling capacitors. The differential limiting output swing with a 500 load is typically 200mVP-P at the fundamental frequency and is temperature stable. Both amplifiers are very stable within their passband and the cascaded performance also exhibits very good stability for any input source impedance. Wide bandwidth SAW filters for spread spectrum applications or any desired source impedance filter implementation can be used for IF filtering before the cascaded amplifiers. The stability is remarkable for such an integrated solution. In fact, in many applications it is possible to remove the bypass pin capacitors with no degradation in stability. The cascaded -1dB and -3dB input limiting sensitivity have been characterized as -79dbm and 84dbm respectively, for a 50 single ended input at 280MHz and with a 47MHz bandwidth interstage bandpass LC filter (refer to Figure 23, Test Diagram). The input sensitivity is determined to a large extent by the bandwidth of the interstage filter and input source impedance. The noise figure for each stage has been characterized at 6dB for a 250 single end input impedance and 9dB for a 50 input impedance. These low noise figures combined
HFA3724
with their high gain, eliminate the need for additional IF gain components. The use of interstage bandpass filtering is suggested to decrease the noise bandwidth of the signal driving the second stage. Excessive broadband noise energy amplified by the first stage will force the last limiting stage to lose some of its effective gain or "limit on the noise". The use of interstage filters with narrower bandwidths will further improve the sensitivity of the cascaded limiter chain. The amplifier differential output impedance is 140 (70 single ended) which gives the user, the ability to design simple wide or narrow LC bandwidth interstage filters, or tailor a desired cascaded gain by using differential attenuators. The filter can be designed with a desired "Q" by using the followIng relationship: Q = Rp/X; where Rp is the parallel combination of 140 source resistance and the load (approximately 500 when using 560 termination as in Figure 23, Test Diagram), and X is the reactance of either L or C at the desired center frequency. Another independent feature of the limiting amplifier is its Receive Signal Strength Indicator (RSSI). A Log-Amp design was developed which resulted in a current output proportional to the input power. The RSSI output voltage is set by summing the two stages output currents, which are full wave rectified signals, to a common resistor to ground. This full wave rectified voltage can then be converted to DC by the use of a filter capacitor in parallel with the resistor (The larger the capacitor value, the less the AC ripple with the expense of longer RSSI settling times). This arrangement gives the user the flexibility to set the dynamic voltage swing to any desired level by an appropriate resistance choice. Each stage has an available on chip 6K low temperature coefficient resistor to ground for current output termination that can be used for convenience. The RSSI gives a 3dBm accurate indication of the receive input power. This accuracy is across a 60dB input dynamic range. The cascaded HFA3724 RSSI slope is of 5.0A/dB.
Quadrature Down Converter
The quadrature down converter mixers are based in a Gilbert cell design. The input signal is routed to both mixers in parallel. With full balanced differential architecture, these mixers are driven by an accurate internal Local Oscillator (LO) chain as described later. Phase and gain accuracy of the output baseband signals are excellent and are a function of the combination of LO accuracy, balanced device design and layout characteristics. Mainly used for down conversion, its input frequency response exceeds 400MHz with a differential voltage gain of 2.5. With a differential input impedance of 1K, the input compression point exceeds 2VP-P, which makes it suitable for use with the hard limiting output from the limiter amplifier chain or any low power external AGC application. The output frequency response is limited to 30MHz for "I" and "Q" baseband signals driving a 4K differential load. The HFA3724 down conversion mixers can generate two 10MHz, 90o apart signals, with the use of proper low pass filtering, and exhibits 4o and 0.5dB of phase and amplitude match for a input CW IF signal of 400MHz and a 2XLO input of 780MHz.
LO Quadrature Generator
The In Phase and Quadrature reference signals are generated by a divide by two chain internal to the device which drives both the up and down conversion mixers. With a fully balanced approach, the phase relationship between the two quadrature signals is within 90o 4o for a wide 10 to 400MHz frequency range. The reference signal input frequency needs to be twice the desired internal reference frequency. The ground referenced 2XLO input is current driven, which makes the input power requirement a function of external components that can be calculated assuming the input impedance of 130. A typical input current value of 200ARMS is the only requirement for reliable LO generation. Figure 24 shows a typical 2XLO input network. Divide by two flip flop architectures for LO generation often require tight control of signal purity or duty cycles. The HFA3724 has an internal duty cycle compensation scheme which eases the requirements of tight controlled duty cycles. In addition, a 50 LO buffer is available to the user for PLL's design reference. It substitutes a divide by two prescaler needed to bring the 2X LO frequency reference down. It is capable to drive 100mVP-P into 50 and its frequency response is from 10MHz to 400MHz corresponding to a 2XLO input frequency response of 20MHz to 800MHz. The LO buffer can be disabled by removing the ground connection to the pin LO GND. The quadrature generator is always enabled for either transmit or receive modes.
47p 50 56
220 44
I RMS = 200A
EQUIVALENT 130
FIGURE 24. MOD LO IN (2XLO) EQUIVALENT CIRCUIT
17
HFA3724 Quadrature Up Converter
The Quadrature up converter mixers are also based on a doubly balanced Gilbert Cell design. "I" and "Q" Up converter signals are summed and buffered together through a single end open collector stage. As with the demodulators, both modulator mixers are driven from the same quadrature LO generator. It features a 4o and 0.5dB of phase and amplitude balance up to 400MHz which are reflected into its SSB characteristics. For "I" and "Q" differential inputs of 500mVP-P, 90o apart, the carrier feedthrough or LO leakage is typical -30dBc into 250 with a sideband suppression of minimum 26dBc at 400MHz. Carrier feedthrough can be further improved by disabling the LO output port (please refer to pin#50 description) or using a DC bias network as in Figure 25. Featuring an output compression level of 1VP-P, the modulator output can generate a CW signal of typical -10dbm into 250 (158mVRMS) when differential DC inputs of 500mVP-P (equivalent to applying 125mV ground referenced levels from the DC bias quiescent point of the device input) are applied to both "I" and "Q" inputs. Four quadrant phase shifts of the carrier output, like in Vector Modulator applications, can be set by proper choice of "I" and "Q" DC differential inputs, such that the square root of the sum of the squares of I and Q is constant. Although specified to drive a 250 load, the HFA3724 modulator open collector output enables user designed output matching networks to suit any application interface. The nominal AC current capability of this port is of 1.3mARMS, which is shared between the termination resistor and the load for I and Q differential DC inputs of 500mVP-P as explained above. (Use 70.7% of this AC capability for I and Q quadrature signals in case of SSB generation).
MOD_TXQ + MOD_TXI + MOD_TXQ -
Programmable Low Pass Filters
These filters are implemented using a 5th order Butterworth architecture. They are multiplexed, i.e., the same filter bank is used for both transmit and receive modes. The filter block, in the transmit mode is set to accept digital (TTL threshold) input data for "I" and "Q" signals and is programmable with 4 frequency cutoffs: (2.2MHz, 4.4MHz, 8.8MHz and 17.8MHz). Digital control pins are used to switch all programmed cutoff modes. The user can design a multi data rate transceiver or simply hardwire these inputs. An external resistor is used to fine tune the cut off frequencies for each setting within 20% of the nominal value. This feature is often needed to fulfill requirements of spectral mask compliance at the antenna output. The "I" and "Q" filter matching is within 2o for phase and 0.25dB for amplitude at the passband. Group delay characteristics follow closely a theoretical 5th order Butterworth design. When in the receive mode, the filters exhibit a 0dB of gain with differential inputs and single ended outputs. In the transmit mode, the digital ground referenced "I" and "Q" input signals are level shifted, shaped and buffered with constant driving differential outputs of 550mVP-P.
Baseband Digital Interfacing
Special precautions must be taken when interfacing the HFA3724 to a digital baseband processor: Large TTL signal swings, overshoots and current spikes, must be carefully considered when dealing with the generation of analog spread spectrum signals which are relatively much smaller in energy per bandwidth. In order to avoid distortion or spurious tones on the analog transmit path, it may be necessary to decrease and/or limit digital excursions as much as possible without compromising the specifications. Figure 26 shows a simplified block diagram of the Transmit digital inputs.
MOD_TXI -
37 38
39
40
1K 50K
1K
1K
1K 50K
43K
43K
FIGURE 25. CARRIER NULL BIASING
18
HFA3724 Coupling Capacitors
VIH TXI R1 LPF_TXI_IN 4.3K VIL 0.1 680 R2 LPF_BYP 1.25V 11 R2 680 13 12 COMPARATOR LEVEL SHIFTER TO I FILTER COMPARATOR LEVEL SHIFTER TO Q FILTER 1.25V FROM BAND GAP
VIH TXQ
Capacitor coupling is used to tie all HFA3724 blocks together. Special bias is used to maintain the DC levels on both ends of coupling pins (capacitors) when the device is changes from Transmitter to a Receiver and vice versa. The capacitance values must be chosen as a compromise to maintain proper frequency response and settling times (when the device is brought up from sleep mode or power down).
R1
4.3K LPF TXQ_IN
VIL
FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT DIGITAL INPUTS
Because of the input comparators high gain, a small overdrive of about 150mV from the reference level of 1.25V is all what is needed to reliably switch and level shift the "I" and "Q" digital signals. An external attenuator comprising of R1 and R2 with termination in the available 1.25V reference voltage pin (LPF BYP) can be calculated based on expected VIH and VIL inputs from a digital interface. Capacitive coupling must be avoided which could affect rise and fall times needed for proper overdrive speed of the comparators. Limiting the digital excursion on those pins greatly reduce the possibility of signal corruption at the transmit chain.
19
HFA3724
AC Electrical Specifications, IF Limiter, Single Stage Individual Performance
PARAMETER IF Frequency Range (Min Limited by Bypass Capacitors) IF Voltage Gain IF Amp. Noise Figure at 250 Source Input Maximum IF Input, Single Ended IF Differential Limiting Output (1st Harmonic at 500 Load) IF Voltage Output Variation at -40dBm to -10dBm Input Range, 500 Load RSSI Slope, Current Output RSSI Slope, Voltage Output at 6K Load RSSI Output Voltage Compliance RSSI DC Offset and Noise Induced Voltage at 6K Load RSSI Absolute Accuracy, VIN = -40dBm RSSI Rise and Fall Time at 50pF Load (-20dBm to -40dBm Input) NOTE: 27. A = Production Tested, B = Based on Characterization, C = By Design TABLE 3. IF LIMITER S11, S22 PARAMETER FREQUENCY 50MHz 100MHz 200MHz 300MHz 400MHz S11 (SINGLE ENDED) 0.96 0.95 0.91 0.84 0.80 -4.0o -8.0o -17.0o -26.0o -33.0o S22 (DIFFERENTIAL) 0.45 0.45 0.47 0.50 0.53 Full Supply Range, TA = 25oC MIN 10 6 400 -0.5 -1.85 -4 TYP 8 1 0.5 500 1.25 MAX 400 30 9 560 0.5 1.85 4 UNITS MHz MHz dB k pF mVP-P dB Degrees Degrees VP-P 0.0o 3.0o 7.0o 9.0o 10.0o SYMBOL IFf IFvG IFNF IFinmax IFVpp IFVppI IFRSSIsi IFRSSIv IFRSSIvc IFRSSIof IFRSSIa IFRSSIt (NOTE 27) TEST LEVEL A A B B A A B A B A A B 25 200 -10 Full Supply Range, TA = 25oC MIN 39 160 -0.5 TYP 45 200 5.7 34 400 MAX 400 7 500 260 +0.5 45 VCC-0.7 600 +10 1 UNITS MHz dB dB mVP-P mVP-P dB A/dB mV/dB V mV % s
AC Electrical Specifications, I/Q Down Converter Individual Performance
PARAMETER Quadrature Demodulator Input Frequency Range Demodulator Baseband I/Q Frequency Range Demodulator Voltage Gain at Frequency Range Demodulator Differential Input Resistance Demodulator Differential Input Capacitance Demodulator Differential Output Level at 4K Load, Input = 200mVP-P Demodulator Amplitude Balance Demodulator Phase Balance at 200MHz Demodulator Phase Balance at 400MHz Demodulator Output Compression Voltage at 4K Load NOTE: 28. A = Production Tested, B = Based on Characterization, C = By Design SYMBOL QDf QDIQf QDg Drin Dcin QDdo QDab QDpb QDPb1 QDoc (NOTE 28) TEST LEVEL B C A C C A A A B B
20
HFA3724
AC Electrical Specifications, I/Q Up Converter and LO Individual Performance
PARAMETER 2XLO Input Frequency Range (2 X Input Range) 2XLO Input Current Range 2XLO Input Impedance Buffered LO Output Voltage, Single Ended Buffered LO Output Impedance Quadrature IF Modulator Output Frequency Range IF Modulator I/Q Input Frequency Range IF Modulator Differential I/Q Max Input Voltage IF Modulator Differential I/Q Input Impedance IF Modulator Differential Input Capacitance IF Modulator I/Q Amplitude Balance IF Modulator I/Q Phase Balance at 200MHz IF Modulator I/Q Phase Balance at 400MHz IF Modulator Output at SSB Into 50, I and Q, 500mVP-P IF Modulator Carrier Suppression (LO Buffer Enabled) IF Modulator Carrier Suppression (LO Buffer Disabled) IF Modulator SSB Sideband Suppression at 200MHz IF Modulator SSB Sideband Suppression at 400MHz IF Output Level Compression Point IF Modulator Intermodulation Suppression NOTE: 29. A = Production Tested, B = Based on Characterization, C = By Design TABLE 4. QUADRATURE MODULATOR S22 PARAMETER FREQUENCY 50MHz 100MHz 200MHz 300MHz 400MHz 0.99 0.98 0.96 0.87 0.82 S22 -2.8o -6.5o -12.3o -25.1o -30.8o SYMBOL LOinf LOinz LOz BLOout BLOoutZ QMLOf QMIQf QMdi QMIQdz Mcin QMIQac QMIQpac QMIQp1 QMIFo QMCs QMCs1 QMSSBs QMSSBs QMIFP1 QMIMsup (NOTE 29) TEST LEVEL B C C A C B C C C C A A B A A A A B C B Full Supply Range, TA = 25oC TYP 200 130 100 50 2.25 4 0.5 30 36 1.0 MAX 800 300 400 30 0.5 2 4 -10.0 UNITS MHz ARMS mVP-P MHz MHz VP-P k pF dB Degrees Degrees dBm dBc dBc dBc dBc VP-P dBc
MIN 20 50 80 10 -0.5 -2 -4 -22 28 28 28 26 26
AC Electrical Specifications, TX Buffer Individual Performance
PARAMETER TX LPF Buffer Serial Data Rate TX LPF Buffer Digital Input Impedance NOTE: 30. A = Production Tested, B = Based on Characterization, C = By Design SYMBOL TXBrat LPFDz
Full Supply Range, TA = 25oC MIN 10 TYP 11 12.5 MAX 22 UNITS MBPS k
(NOTE 30) TEST LEVEL A C
21
HFA3724
AC Electrical Specifications, RX/TX 5TH Order LPF Individual Performance
PARAMETER TX/RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 0 TX/RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 0 TX/RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 1 TX/RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 1 TX/RX LPF Sel0, Sel1 Tuning Speed TX/RX LPF 3dB Bandwidth Tuning LPF Tune Nominal Resistance RX LPF Voltage Gain RX LPF Single Ended Output Voltage Swing at 2k Load RX LPF Differential Input Impedance TX LPF Differential Digital Output Voltage Swing at 4k Load TX/RX I/Q Channel Amplitude Match TX/RX I/Q Channel Phase Match TX/RX LPF Total Harmonic Distortion NOTE: 31. A = Production Tested, B = Based on Characterization, C = By Design TABLE 5. LOW PASS FILTER PROGRAMMING AND TUNING INFORMATION MODE BW0 BW1 BW2 BW3 LPF SEL1 0 0 1 1 LPF SEL0 0 1 0 1 f3dB (NOMINAL RTUNE) 2.2MHz 4.4MHz 8.8MHz 17.6MHz SYMBOL LPF3db0 LPF3db1 LPF3db2 LPF3db3 LPFsp LPFtu LPFTr LPFg LPFRXar LPFRXzi LPFTXo LPFIQm LPFIQpm LPFTHD (NOTE 31) TEST LEVEL A A A A B A B A B A A A A B Full Supply Range, TA = 25oC MIN 1.8 3.6 7.4 14.8 -20 -1.0 4 450 -0.5 -3 TYP 2.20 4.40 8.80 17.60 787 0 500 5 550 3 MAX 2.4 4.8 9.6 19.2 1 +20 1.0 670 0.5 3 UNITS MHz MHz MHz MHz s % dB mVP-P k mVP-P dB Degrees %
f 3dBNOMINAL 787 f TUNED 3dB = --------------------------------------------------R TUNE
22
HFA3724
TYPICAL f3dB vs RTUNE PERCENT OF NOMINAL FREQUENCY +20%
-20% -30 -25 -20 -15 -10 -5 0 +5 +10 +15 +20 +25 +30
[(787 - RTUNE)/RTUNE] * 100%
FREQUENCY 20% Low Nominal 20% High FIGURE 27.
RTUNE 984 787 656
Typical Performance Curves, Individual Blocks
1dB/DIV. 5.5V 0.25dB/DIV. 7dB 85o
45dB 85o 25o -40o 6dB
25o
2.7V
-40o
40dB 85o 25o -40o 10M 100M 500MHz 5dB
2.5V
4V VCC
5.5V
FIGURE 28. SINGLE STAGE LIMITER GAIN vs FREQUENCY AND TEMPERATURE, VCC = 2.7V, 5.5V
FIGURE 29. SINGLE STAGE LIMITER NOISE FIGURE vs VCC AND TEMPERATURE, RS = 250, FREQUENCY = 300MHz
23
HFA3724 Thin Plastic Quad Flatpack Packages (LQFP)
D D1 -D-
Q80.14x14 (JEDEC MS-026BEC ISSUE C)
80 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE SYMBOL A A1 A2 INCHES MIN 0.002 0.054 0.009 0.009 0.626 0.547 0.626 0.547 0.018 80 0.026 BSC MAX 0.062 0.005 0.057 0.014 0.012 0.634 0.555 0.634 0.555 0.029 MILLIMETERS MIN 0.05 1.35 0.22 0.22 15.90 13.90 15.90 13.90 0.45 80 0.65 BSC MAX 1.60 0.15 1.45 0.38 0.33 16.10 14.10 16.10 14.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- .
0.13 A-B S 0.005 M C DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING
-AE E1
-B-
b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.08 0.003 -C-
E1 L N e
-H-
4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 11o-13o A2 A1
0.09/0.20 0.004/0.008
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
24

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